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Silicon Labs /BGM220SC22HNA /HFXO0_S /XTALCFG

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Interpret as XTALCFG

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https://regviz.com/r/Silicon Labs/EFR32BG22C224F512GM32/HFXO0_S/XTALCFG#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0COREBIASSTARTUPI 0COREBIASSTARTUP 0CTUNEXISTARTUP 0CTUNEXOSTARTUP 0 (T16US)TIMEOUTSTEADY 0 (T8US)TIMEOUTCBLSB

TIMEOUTCBLSB=T8US, TIMEOUTSTEADY=T16US

Description

No Description

Fields

COREBIASSTARTUPI

Intermediate Startup Core Bias Current
COREBIASSTARTUP

Startup Core Bias Current
CTUNEXISTARTUP

Startup Tuning Capacitance on XI
CTUNEXOSTARTUP

Startup Tuning Capacitance on XO
TIMEOUTSTEADY

Steady State Timeout

0 (T16US): The steady state timeout is set to 16 us minimum. The maximum can be +40%.

1 (T41US): The steady state timeout is set to 41 us minimum. The maximum can be +40%.

2 (T83US): The steady state timeout is set to 83 us minimum. The maximum can be +40%.

3 (T125US): The steady state timeout is set to 125 us minimum. The maximum can be +40%.

4 (T166US): The steady state timeout is set to 166 us minimum. The maximum can be +40%.

5 (T208US): The steady state timeout is set to 208 us minimum. The maximum can be +40%.

6 (T250US): The steady state timeout is set to 250 us minimum. The maximum can be +40%.

7 (T333US): The steady state timeout is set to 333 us minimum. The maximum can be +40%.

8 (T416US): The steady state timeout is set to 416 us minimum. The maximum can be +40%.

9 (T500US): The steady state timeout is set to 500 us minimum. The maximum can be +40%.

10 (T666US): The steady state timeout is set to 666 us minimum. The maximum can be +40%.

11 (T833US): The steady state timeout is set to 833 us minimum. The maximum can be +40%.

12 (T1666US): The steady state timeout is set to 1666 us minimum. The maximum can be +40%.

13 (T2500US): The steady state timeout is set to 2500 us minimum. The maximum can be +40%.

14 (T4166US): The steady state timeout is set to 4166 us minimum. The maximum can be +40%.

15 (T7500US): The steady state timeout is set to 7500 us minimum. The maximum can be +40%.
TIMEOUTCBLSB

Core Bias LSB Change Timeout

0 (T8US): The core bias LSB change timeout is set to 8 us minimum. The maximum can be +40%.

1 (T20US): The core bias LSB change timeout is set to 20 us minimum. The maximum can be +40%.

2 (T41US): The core bias LSB change timeout is set to 41 us minimum. The maximum can be +40%.

3 (T62US): The core bias LSB change timeout is set to 62 us minimum. The maximum can be +40%.

4 (T83US): The core bias LSB change timeout is set to 83 us minimum. The maximum can be +40%.

5 (T104US): The core bias LSB change timeout is set to 104 us minimum. The maximum can be +40%.

6 (T125US): The core bias LSB change timeout is set to 125 us minimum. The maximum can be +40%.

7 (T166US): The core bias LSB change timeout is set to 166 us minimum. The maximum can be +40%.

8 (T208US): The core bias LSB change timeout is set to 208 us minimum. The maximum can be +40%.

9 (T250US): The core bias LSB change timeout is set to 250 us minimum. The maximum can be +40%.

10 (T333US): The core bias LSB change timeout is set to 333 us minimum. The maximum can be +40%.

11 (T416US): The core bias LSB change timeout is set to 416 us minimum. The maximum can be +40%.

12 (T833US): The core bias LSB change timeout is set to 833 us minimum. The maximum can be +40%.

13 (T1250US): The core bias LSB change timeout is set to 1250 us minimum. The maximum can be +40%.

14 (T2083US): The core bias LSB change timeout is set to 2083 us minimum. The maximum can be +40%.

15 (T3750US): The core bias LSB change timeout is set to 3750 us minimum. The maximum can be +40%.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data